1. Field of the Invention
This invention relates to a communication system and, more particularly, to clock recovery circuits within nodes of the communication system that avoid producing a clock frequency outside an acceptable range whenever the clock recovery circuits recover a clocking signal from the communication system that is not immediately derived from a node having a clocking signal master.
2. Description of the Related Art
A communication system is generally well known as containing at least two nodes interconnected by a transmission line. Each transmission line can accommodate not only digital data, but also data that can arrive as voice data, audio data, video data, or bursts of data derived from a computer domain. An optimal transmission line is therefore one that can receive information from a multimedia device, herein defined as any hardware and/or software module that can transfer information in whatever form upon the network. The transmission line can either be a copper wire, optical fiber, or a wireless transmission medium.
There are many types of multimedia devices. For example, a multimedia device can include a telephone, a compact disc (CD) player, a digital video disc (DVD) player, a computer, an amplifier, a speaker, or any device that can send and receive different types of data across the transmission line of the network.
Popular types of data sent or received by multimedia devices include streaming data or packetized data. Streaming data is data that has a temporal relationship between samples produced from a source port onto the network. That relationship must be maintained in order to prevent perceptible errors, such as gaps or altered frequencies at the destination port. Packetized data need not maintain the sample rate or temporal relationship of that data and, instead, can be sent as disjointed bursts across the transmission line.
Depending on the frequency difference between the local clock of the source port (or destination port) and the network frame transfer rate, streaming data can be sent either synchronously or isochronously across the network. If the sample rate (i.e., “fs”) local to the node is the same frequency as the frame synchronization rate (i.e., “FSR”) of the transmission line, then the streaming data can be sent synchronously across the network. In many instances, FSR is dissimilar from fs. Thus, the sample rate must be changed (or converted), or the streaming data must be sent isochronously across the network, where isochronous transfer protocols are used to accommodate the frequency differences in order to prevent perceptible gaps, errors, jitter, or echo. Regardless of how data is being sent across a transmission line, the data must nonetheless be referenced to a clock. The clock (sometimes known as a master clock) placed in one node synchronizes the transmission from that node across the transmission line.
Referring to FIG. 1, a communication system 10 is shown. System 10 includes a plurality of nodes 12. Each node can include a transceiver, an input/output port and a multimedia device. Data sent across a transmission line 14 can, therefore, be used by a multimedia device within the destination node. FIG. 1 illustrates transfer of data from node 12d, beginning with a preamble at time T1, through each of the nodes 12c, 12b, and 12a, with substantially similar delay (ΔT0) through each node.
FIG. 1 illustrates typical clock recovery mechanisms used within nodes 12. Generally speaking, one node (e.g., node 12d) of communication system 10 has a local master clock which can be derived from an external crystal 18, for example. Data transferred from node 12d can be synchronized to the master clocking signal as it traverses the transmission line. The master clocking signal may be recovered by a phase-locked loop, for example, at each of the various slave nodes 12a-c. The phase-locked loop (“PLL”) 20, therefore, produces a recovered clock that is used to synchronize a digital subsystem, such as a local microcontroller 22.
The clock recovery circuit and, more particularly, PLL 20 within each of the slave nodes simply reconstructs the master clock 18 dedicated to a particular node 12d. Communication system 10 thereby requires that one node have a dedicated clock master (i.e., a master node) and all other nodes are absent a clock master (i.e., all other nodes are slave nodes). If two nodes employ a clock master, then one master might drift in frequency relative to another. The result might be perceptible gaps, errors, or echo at the destination node relative to the source node transmission. It is important to establish one master node and all other nodes as slave nodes. It is sometimes difficult at best to determine which node should be the master. The problem is compounded if the same node always remains as the master, yet the master clock within that node drifts from its targeted frequency.
FIG. 2 illustrates a plausible outcome if the clock master were to drift or altogether disappear. In the latter instance, each node would operate as a slave, and the frequency by which bits of data are transferred across the transmission link would fluctuate upward or downward with seemingly little if any constraint. As shown, preamble N followed by frame N dispatched from node D will be delayed as it passes through node C. Likewise, the preamble N and frame N will be further delayed through node B and, finally, through node A. Node D preferably contains a buffer 26 (FIG. 1) that synchronizes the frame of data received from node A and places that frame in the next frame location within frame N+1, as shown by arrow 28.
While each node has a corresponding delay, ΔT0, the delay through the master node, ΔTBUF, is purposely timed so that it is synchronized to the next preamble N+1. The amount of delay ΔTBUF is, therefore, dependent on the buffer being clocked synchronous with the local master clock, and that the master clock purposely synchronizes the preambles of succeeding frames. If there is no local master clock, then ΔTBUF can fluctuate or altogether disappear. The fluctuation is passed from node to node as each PLL attempts to lock yet fails temporarily. The periodic unlock at each PLL, before the PLL can again retain lock travels around the ring, and is hereinafter referred to as a “rotating unlock” condition.
While it is important to avoid the all slave circumstance and the ensuing rotating unlock condition, not all communication systems can be assured of having a dedicated clocking master at all times. For example, depending on how the nodes are compiled onto the communication system, there may be instances in which the integrated circuits provided by manufacturers at various nodes simply do not contain master capabilities. Conversely, while each node might have master capability, a configuration register within the corresponding nodes may not be properly set to enable a single clocking master. Instead, possibly competing clocking masters might be established or no clocking masters whatsoever. Thus, while the flexibility of having an integrated circuit be either a master or slave is beneficial, it is not always possible to ensure the software program which sets the integrated circuits as a master or a slave is properly functioning. Certainly, manufacturers do no choose to make integrated circuits that operate solely as a master or solely as a slave, and application engineers do not always have the luxury of deciding which node should be the master and which remaining nodes should be the slave if, indeed, software and/or hardware configurations malfunction.
It would be desirable to introduce a communication system that, regardless of any malfunction, always assures the data transferred throughout the transmission line does not exceed or is less than a threshold frequency of a reference clocking master. It is inconsequential where the reference clocking master is derived, or whether instances of all slave and rotating unlock occur. Provided the unlock conditions do not rise to the level of inappropriate clocking frequencies outside an acceptable range, a dedicated clocking master within a specific node is purposely avoided for reasons set forth below.